In many cases the data processing speed of a computer system can be greatly enhanced by providing one or more additional processors to form a multiprocessor system in which a common or central RAM memory is shared. However, the sharing of resources, particularly the memory, results in conflicts between the processors' various memory reference requests, such that if the memory and the memory access control logic is not properly designed much of the potential increase in efficiency and economy of the system can be lost to access delays.
Minimizing conflicts and delays in accessing a shared memory is typically accomplished in two different but cooperative ways. One way is to segment the shared memory into many independently addressable banks such that each reference to a bank ties up a relatively small percentage of the memory, leaving the rest of the memory accessible. This approach, however, entails an increase in the complexity and thus size and cost of the memory, and can also impose limitations on the speed at which each reference may be accomplished.
The other approach to minimizing memory reference delays involves the interface between each processor and the available memory access paths, and the treatment of conflicting requests to memory either between individual ports in a processor or between different processors. As may be readily appreciated, this approach must be cooperative with the former approach as the design of the interface must correspond to the number of independent access paths between the memory and the processors.
Ideally, the memory interface should provide for maximum utilization of the available memory access paths and that each processor has substantially equal accessibility to the memory at most times, particularly where there is no master-slave relationship between the processors. In addition, it is desireable that memory conflicts be resolved in as few system clock periods as possible so that reference start up time and data buffering requirements are held to a minimum. The attainment of these goals is, however, restrained by the cost and particularly the quantity of logic which may be employed. In particular, in the case of high-speed vector processing machines there are tight restrictions on the space which may be alotted to interface circuits due to the necessity to bring all processors into close proximity to the memory in order that propagation delays be minimized. In addition, it is desireable that wiring requirements be held down.
As is well appreciated by those skilled in the art, attaining an efficient, economical and workable memory interface becomes increasingly difficult as the number of processors is increased. Those designs which may be quite efficient in a dual processor system may be totally unuseable in a four processor system because of the geometric increases in logic which are needed to adapt a dual processor scheme to a larger number of processors. Moreover, increasing the number of processors typically increases the nominal distance between a given processor and the memory, increasing signal propagation delay and placing further restraints on the number of logic levels which may be employed.